From 45cb3060c5bbcd83f630b27b391c331eb27e076d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 23 Apr 2026 09:06:18 +0530 Subject: [PATCH 1/2] Revert "Revert "FROMLIST: PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller"" Commit bf62c12d1523 ("Revert "FROMLIST: PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller"") was applied due to excessive AER logging and functional breakage after INTx fallback. The AER issue is now mitigated by disabling L0s, so restore the original behavior and remove MSI/MSI-X capabilities from Root Ports using iMSI-RX. This reverts commit bf62c12d1523 ("Revert "FROMLIST: PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller""). Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 60620cc0dedcf..29cbb9ed26a59 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1106,6 +1106,16 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) dw_pcie_dbi_ro_wr_dis(pci); + /* + * If iMSI-RX module is used as the MSI controller, remove MSI and + * MSI-X capabilities from PCIe Root Ports to ensure fallback to INTx + * interrupt handling. + */ + if (pp->has_msi_ctrl) { + dw_pcie_remove_capability(pci, PCI_CAP_ID_MSI); + dw_pcie_remove_capability(pci, PCI_CAP_ID_MSIX); + } + return 0; } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); From 3bb5cae9c6e7a7f467ea3bc6a88f4dac3d7fd868 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 19 Apr 2026 17:39:34 +0800 Subject: [PATCH 2/2] FROMLIST: PCI: qcom: Disable ASPM L0s for SA8775P Commit f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller") removed MSI/MSI-X capabilities from the Root Port on platforms using iMSI-RX (including SA8775P, which has no msi-parent/msi-map in DT). This causes PME and AER service drivers to fall back from MSI to INTx. There are lot of AER's seen after this change, the reason for this AER's can be board specific, and recently discovered refgen voting required by phy driver. [ 13.069528] pcieport 0000:00:00.0: PME: Signaling with IRQ 332 [ 13.082436] pcieport 0000:00:00.0: AER: enabled with IRQ 332 [ 13.082447] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0 [ 13.101347] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID) [ 13.111281] pci 0000:01:00.0: device [17cb:1103] error status/mask=00001000/0000e000 [ 13.111284] pci 0000:01:00.0: [12] Timeout [ 13.111313] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0 [ 13.130512] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID) [ 13.130514] pcieport 0000:00:00.0: device [17cb:0115] error status/mask=00001000/0000e000 [ 13.130516] pcieport 0000:00:00.0: [12] Timeout Fix this temporarly on SA8775P/Lemans platform by adding no_l0s = true to cfg_1_34_0 for SA8775P, so that PCI_EXP_LNKCAP_ASPM_L0S is cleared from the Root Port and ASPM L0s is prevented from being negotiated. Fixes: f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller") Assisted-by: Claude:claude-4-6-sonnet Link: https://lore.kernel.org/all/20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com/ Signed-off-by: Shawn Guo --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 83e973623f55b..6aec2fce916a1 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1483,6 +1483,7 @@ static const struct qcom_pcie_cfg cfg_1_9_0 = { static const struct qcom_pcie_cfg cfg_1_34_0 = { .ops = &ops_1_9_0, .override_no_snoop = true, + .no_l0s = true, }; static const struct qcom_pcie_cfg cfg_2_1_0 = {