fix(igc): stabilize i225 phy bring-up#680
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ytakano merged 4 commits intotier4:mainfrom Apr 21, 2026
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Align the Awkernel I225 bring-up path more closely with the BSD igc drivers and improve diagnostics around the PHY reset path. This change makes the MAC reset path tolerant of auto-read completion timeouts, initializes and synchronizes the MDIC PHY address, powers the PHY up before reading its ID, and clears GO_LINKD/ULP before attempting the hardware reset. The PHY reset path now retries once, logs the relevant control/status registers, and treats a missing RST_COMPL bit as non-fatal when direct MDIC reads show that the PHY is already responding. On the driver side, tick-based link polling was added so link state can advance even when only the periodic path runs, and link transitions now log speed/duplex changes. In hardware testing over /dev/ttyUSB0, the previous hard timeout message was replaced by a benign "PHY reset completion bit did not assert, but PHY responded" diagnostic, and the port reached "Up (Full Duplex)" during boot.
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Pull request overview
Stabilizes Intel I225 PHY bring-up by aligning reset/MDIO initialization behavior with BSD igc drivers and improving link-state diagnostics in the Awkernel driver.
Changes:
- Make the MAC/PHY reset and PHY reset-completion handling more tolerant (retry, extra register diagnostics, non-fatal when PHY is responsive).
- Synchronize MDIC PHY address and power up the PHY before attempting PHY-ID reads.
- Add tick-based link polling and log link transitions (speed/duplex and status changes).
Reviewed changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated 2 comments.
| File | Description |
|---|---|
awkernel_drivers/src/pcie/intel/igc/igc_phy.rs |
Adds MDIC PHY address sync helper; hardens PHY reset path (ULP/GO_LINKD clearing, retry, improved diagnostics). |
awkernel_drivers/src/pcie/intel/igc/i225.rs |
Tolerates auto-read-done timeout; syncs MDIC PHY address; clears low-power/link-down bits; powers PHY before ID read. |
awkernel_drivers/src/pcie/intel/igc.rs |
Adds tick-driven link polling when no LSC interrupt; logs link up/down and status changes. |
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Address the review feedback on PR tier4#680. Replace the unbounded 100,000-iteration 1us busy-wait in igc_phy_hw_reset_generic with a two-phase reset-completion poll: a short tight loop for the fast-success case followed by a 1ms backoff loop to avoid burning CPU during bring-up while preserving the existing MDIC-based fallback when RST_COMPL does not assert. Also replace the PHPM magic number 0x0400 in i225 bring-up with the shared IGC_I225_PHPM_ULP constant so the low-power bit definition stays named and centralized. Verification: - make fmt - make x86_64 RELEASE=1 - rebooted the physical x86_64 target over /dev/ttyUSB0 at 38400 baud - confirmed the rebuilt kernel booted via TFTP and igc still reached link up
atsushi421
reviewed
Apr 20, 2026
- Elevate PHY reset timeout log from debug to warn for visibility - Add write_flush after IGC_MDICNFG write in igc_sync_mdic_phy_addr - Add doc comments to igc_sync_mdic_phy_addr and igc_poll_link - Simplify redundant should_poll_link condition to irq.is_none() Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
atsushi421
approved these changes
Apr 21, 2026
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Description
Align the Awkernel I225 bring-up path more closely with the BSD igc drivers and improve diagnostics around the PHY reset path.
This change makes the MAC reset path tolerant of auto-read completion timeouts, initializes and synchronizes the MDIC PHY address, powers the PHY up before reading its ID, and clears GO_LINKD/ULP before attempting the hardware reset. The PHY reset path now retries once, logs the relevant control/status registers, and treats a missing RST_COMPL bit as non-fatal when direct MDIC reads show that the PHY is already responding.
On the driver side, tick-based link polling was added so link state can advance even when only the periodic path runs, and link transitions now log speed/duplex changes. In hardware testing over a serial console, the previous hard timeout message was replaced by a benign "PHY reset completion bit did not assert, but PHY responded" diagnostic, and the port reached "Up (Full Duplex)" during boot.
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How was this PR tested?
Notes for reviewers